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mos integrated circuit pd17p246 description the pd17p246 is a model of the pd17246 with a one-time prom instead of an internal mask rom. since the user can write programs to the pd17p246, it is ideal for experimental production or small-scale production of the pd17240, 17241, 17242, 17243, 17244, 17245, or 17246 systems. when reading this document, also read the documents related to the pd17240, 17241, 17242, 17243, 17244, 17245, and 17246. detailed function descriptions are provided in the following user? manual. be sure to read them before designing. pd172 subseries user's manual: u12795e features pin compatible with pd17240, 17241, 17242, 17243, 17244, 17245, and 17246 (except prom programming function) carrier generator for infrared remote controller (rem output) 17k architecture: general-purpose register method program memory (one-time prom): 32 kb (16,384 16) data memory (ram): 447 4 bits ram retention detector low-voltage detector supply voltage: v dd = 2.2 to 3.6 v (4 s) applications preset remote controllers, toys, and portable systems ordering information part number package pd17p246m1mc-5a4 30-pin plastic ssop (7.62 mm (300)) document no. u15215ej1v0ds00 (1st edition) date published may 2003 n cp(k) printed in japan 4-bit single-chip microcontroller for small general-purpose infrared remote controller data sheet the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. the mark shows major revised points.
pd17p246 2 data sheet u15215ej1v0ds pin configuration (top view) (1) normal operating mode ? 30-pin plastic ssop (7.62 mm (300)) pd17p246m1mc-5a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 p0d 2 p0d 3 p1b 0 /int p0e 0 p0e 1 p0e 2 p0e 3 rem v dd x out x in gnd reset p1a 0 p1a 1 p1a 2 p0d 1 p0d 0 p0c 3 p0c 2 p0c 1 p0c 0 p0b 3 p0b 2 p0b 1 p0b 0 p0a 3 p0a 2 p0a 1 p0a 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gnd: ground int: external interrupt request signal input p0a 0 to p0a 3 : input port (cmos input with pull-up resistor) p0b 0 to p0b 3 : i/o port (cmos input with pull-up resistor/n-ch open-drain output) p0c 0 to p0c 3 : i/o port (cmos input with pull-up resistor/n-ch open-drain output) p0d 0 to p0d 3 : i/o port (cmos input with pull-up resistor/n-ch open-drain output) p0e 0 to p0e 3 : i/o port (when key matrix is used: cmos input with pull-up resistor/n-ch open- drain output, when key matrix is not used: cmos input/push-pull output) p1a 0 to p1a 2 : i/o port (when key matrix is used: cmos input/n-ch open-drain output, when key matrix is not used: cmos input/push-pull output) p1b 0 : input port (cmos input) rem: remote controllers output (cmos push-pull output) reset: reset input v dd : power supply x in , x out : resonator connection
pd17p246 3 data sheet u15215ej1v0ds (2) prom programming mode 30-pin plastic ssop (7.62 mm (300)) pd17p246m1mc-5a4 caution contents in parentheses indicate how to handle unused pins in prom programming mode. l: connect to gnd via a resistor (470 ? ) separately. open: leave unconnected. clk: clock input for prom d 0 to d 7 : data input/output for prom gnd: ground md 0 to md 3 : mode select input for prom v dd : power supply v pp : power supply for prom writing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d 2 d 3 v pp (open) v dd (open) clk gnd (l) (open) (open) (open) d 1 d 0 d 7 d 6 d 5 d 4 md 3 md 2 md 1 md 0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 (l) (l)
pd17p246 4 data sheet u15215ej1v0ds block diagram remark ( ): during prom programming mode p0a 0 p0a 1 p0a 2 p0a 3 p0a p0b 0 (md 0 ) p0b 1 (md 1 ) p0b 2 (md 2 ) p0b 3 (md 3 ) p0b p0c 0 (d 4 ) p0c 1 (d 5 ) p0c 2 (d 6 ) p0c 3 (d 7 ) p0c p0d 0 (d 0 ) p0d 1 (d 1 ) p0d 2 (d 2 ) p0d 3 (d 3 ) p0d p0e 0 p0e 1 p0e 2 p0e 3 p0e p1a 0 p1a 1 p1a 2 p1b 0 p1a p1b rf system reg. alu osc cpu clock rem int/p1b 0 (v pp ) v dd gnd x in (clk) x out instruction decoder power supply circuit remote control divider 8-bit timer interrupt controller reset reset controller program counter stack (5 levels) ram 447 4 bits one-time prom 16,384 16 bits basic interval/ watchdog timer
pd17p246 5 data sheet u15215ej1v0ds contents 1. differences between pd17246 and pd17p246 .............................................................. 6 2. pin functions ................................................................................................................ .............. 7 2.1 normal operating mode ....................................................................................................... ................ 7 2.2 prom programming mode ....................................................................................................... ........... 10 2.3 i/o circuits ................................................................................................................ ............................. 11 2.4 connection of unused pins ................................................................................................... .............. 13 2.5 notes on using the reset and int pins ....................................................................................... .... 13 3. writing and verifying one-time prom (program memory) ....................................... 14 3.1 operating mode when writing/verifying program memory ............................................................. 14 3.2 program memory writing procedure ............................................................................................ ...... 15 3.3 program memory reading procedure ............................................................................................ .... 16 4. electrical specifications .................................................................................................... 17 5. package drawing .............................................................................................................. ....... 25 6. recommended soldering conditions ............................................................................... 26 appendix development tools .................................................................................................... 27
pd17p246 6 data sheet u15215ej1v0ds 1. differences between pd17246 and pd17p246 the pd17p246 is equipped with one-time prom to which data can be written by the user instead of the internal mask rom (program memory) of the pd17246. table 1-1 shows the differences between the pd17246 and pd17p246. the cpu functions and internal hardware of the pd17p246, 17240, 17241, 17242, 17243, 17244, 17245, and 17246 are identical. therefore, the pd17p246 can be used to evaluate the program developed for the pd17240, 17241, 17242, 17243, 17244, 17245, and 17246 system. note, however, that some of the electrical specifications such as supply current and low-voltage detection voltage of the pd17p246 are different from those of the pd17240, 17241, 17242, 17243, 17244, 17245, and 17246. table 1-1. differences between pd17246 and pd17p246 product name pd17p246 pd17246 item program memory one-time prom mask rom 32 kb (16,384 16) (0000h to 3fffh) data memory 447 4 bits low-voltage detector note 1 provided any (mask option) v pp pin, operation mode select pin provided not provided instruction execution time note 2 4 s (v dd = 2.2 to 3.6 v) 4 s (v dd = 2.0 to 3.6 v) supply voltage note 2 v dd = 2.2 to 3.6 v v dd = 2.0 to 3.6 v package 30-pin plastic ssop (7.62 mm (300)) notes 1. although the circuit configuration is identical, the electrical characteristics differ depending on the product. 2. when f x = 4 mhz and high-speed mode operation is set.
pd17p246 7 data sheet u15215ej1v0ds 2. pin functions 2.1 normal operating mode (1/3) pin no. symbol function output form after reset 28 p0d 0 these pins constitute a 4-bit i/o port which can be set in the input n-ch low-level 29 p0d 1 or output mode in 4-bit units (group i/o). open-drain output 1 p0d 2 in the input mode, these pins serve as cmos input pins with a 2 p0d 3 pull-up resistor, and can be used as the key return input lines of a key matrix. the standby status must be released when at least one of the input lines goes low. in the output mode, these pins are used as n-ch open-drain output pins and can be used as the output lines of a key matrix. 3 p1b 0 /int this is an input port pin. whether this pin functions as the p1b 0 p1b 0 input pin or the int pin can be selected by the register file. (when key p1b 0 matrix is not this is a 1-bit cmos input port. used and no this port can be used to input a key return signal when a key resistor matrix is used. at this time, whether a pull-up/down resistor is connected) connected to this port and the standby mode release condition (whether it is released when this pin is high or low) can be selected. 1. if connection of a resistor is specified and if it is specified that the standby mode is released when this pin goes low ... a pull-up resistor is connected. if a low level is input to the p1b 0 pin, the standby mode is released. 2. if connection of a resistor is specified and if it is specified that the standby mode is released when this pin goes high ... a pull-down resistor is connected. if a high level is input to the p1b 0 pin, the standby mode is released. 3. if connection of a resistor is not specified and if it is specified that the standby mode is released when this pin goes low (or high) ... no resistor is connected. if a low (or high) level is input to the p1b 0 pin, the standby mode is released. if a key matrix is not used, whether a resistor is connected and whether a pull-up or pull-down resistor is connected can be selected. int this is an external interrupt request signal. it can also be used to release the standby mode if an external interrupt request signal is input to this pin while the int pin interrupt enable flag (ip) is set.
pd17p246 8 data sheet u15215ej1v0ds 2.1 normal operating mode (2/3) pin no. symbol function output form after reset 4 p0e 0 these pins constitute a 4-bit i/o port that can be set in the input or when key cmos input 5 p0e 1 output mode in 1-bit units. matrix is (when key 6 p0e 2 if this port is set in the input mode when a key matrix is used, it used: n-ch matrix is not 7 p0e 3 functions as a cmos input port with a pull-up resistor and can be open-drain, used and no used to input key return signals. if one of the pins of this port when key resistor goes low, the standby mode is released. matrix is not connected) if this port is set in the output mode when a key matrix is used, it used: cmos functions as an n-ch open-drain output port and can be used to push-pull output key matrix signals. if this port is set in the input mode when a key matrix is not used, it functions as a cmos input port to/from which a resistor can be connected or disconnected in 1-bit units. if this port is set in the output mode when a key matrix is not used, it functions as a high- current cmos output port. 8 rem outputs transfer signal for infrared remote controller. cmos low-level active-high output. push-pull output 9v dd power supply 10 x out connects ceramic resonator for system clock oscillation (oscillation 11 x in stops) 12 gnd ground 13 reset reset input turns on pull-down resistor if poc or watchdog timer overflows input and if the stack pointer overflows or underflows, and resets the system. usually, the pull-down resistor is on.
pd17p246 9 data sheet u15215ej1v0ds 2.1 normal operating mode (3/3) pin no. symbol function output form after reset 14 p1a 0 these pins constitute a 3-bit i/o port that can be set in the input or when key cmos input 15 p1a 1 output mode in 1-bit units. matrix is (when key 30 p1a 2 if this port is set in the input mode when a key matrix is used, it used: n-ch matrix is not functions as a cmos input port and can be used to input key open-drain, used and return signals. at this time, whether a pull-up/down resistor is when key no resistor connected to this port and the standby mode release condition matrix is not connected) (whether it is released when this pin is high or low) can be used: cmos selected in 1-bit units push-pull 1. if connection of a resistor is specified and if it is specified that the standby mode is released when this port goes low ... a pull-up resistor is connected. if a low level is input to the set pin, the standby mode is released. 2. if connection of a resistor is specified and if it is specified that the standby mode is released when this port goes high ... a pull-down resistor is connected. if a high level is input to the set pin, the standby mode is released. 3. if connection of a resistor is not specified and if it is specified that the standby mode is released when this port goes low (or high) ... no resistor is connected. if a low (or high) level is input to the set pin, the standby mode is released. if this port is set in the output mode when a key matrix is used, it functions as an n-ch open-drain output port and can be used to output key matrix signals. if this port is set in the input mode when a key matrix is not used, it functions as a cmos input port. connection of a resistor to this port and whether a pull-up or pull- down resistor is connected to the port can be selected in 1-bit units. if this port is set in the output mode when a key matrix is not used, it functions as a high-current cmos output port. 16 p0a 0 these pins are cmos input pins with a 4-bit pull-up resistor. cmos input 17 p0a 1 they can be used as the key return input lines of a key matrix. with pull-up 18 p0a 2 if any one of these pins goes low, the standby status is released. resistor 19 p0a 3 20 p0b 0 these pins constitute a 4-bit i/o port that can be set in the input or n-ch cmos input 21 p0b 1 output mode in 1-bit units. open-drain with pull-up 22 p0b 2 in the input mode, these pins are cmos input pins with a pull-up resistor 23 p0b 3 resistor, and can be used as the key return input lines of a key matrix. the standby status is released when at least one of these pins goes low. in the output mode, they serve as n-ch open-drain output pins and can be used as the output lines of a key matrix. 24 p0c 0 these pins constitute a 4-bit i/o port that can be set in the input or n-ch low-level 25 p0c 1 output mode in 4-bit units (group i/o). open-drain output 26 p0c 2 in the input mode, these pins are cmos input pins with a pull-up 27 p0c 3 resistor, and can be used as the key return input lines of a key matrix. the standby status is released when at least one of these pins goes low. in the output mode, they serve as n-ch open-drain output pins and can be used as the output lines of a key matrix.
pd17p246 10 data sheet u15215ej1v0ds 2.2 prom programming mode pin no. symbol function output form after reset 3v pp power supply for prom programming. apply +12.5 v to this pin as the program voltage when writing/ verifying program memory. 9v dd power supply. apply +6 v to this pin when writing/verifying program memory. 11 clk inputs clock for prom programming. 12 gnd ground. 20 md 0 input pins used to select operating mode when prom is input ?? programmed. 23 md 3 24 d 4 input/output 8-bit data for prom programming cmos input ?? push-pull 27 d 7 28 d 0 29 d 1 1d 2 2d 3 remark the other pins are not used in the prom programming mode. how to handle the other pins are described in pin configuration (2) prom programming mode .
pd17p246 11 data sheet u15215ej1v0ds 2.3 i/o circuits the equivalent i/o circuit for each pd17p246 pin is shown below. figure 2-1. i/o circuits (1/2) (4) p1a (5) p1b (1) p0a (2) p0b, p0c, p0d (3) p0e v dd input buffer selector n-ch p-ch v dd output disable input buffer data output latch p-ch n-ch v dd data data pull-up/ pull-down resistor stop clear level selector input buffer p-ch p-ch n-ch pull-up resistor output latch input buffer data data data output disable selector v dd v dd key matrix use/non- use resistor p-ch n-ch key matrix use/non- use resistor pull-up/ pull-down resistor output latch stop clear level input buffer data data data data output disable selector p-ch n-ch v dd v dd
pd17p246 12 data sheet u15215ej1v0ds figure 2-1. i/o circuits (2/2) (6) reset (7) int (8) rem p-ch n-ch v dd data output disable p-ch reset signal input buffer schmitt-triggered input with hysteresis characteristics v dd n-ch input buffer schmitt-triggered input with hysteresis characteristics
pd17p246 13 data sheet u15215ej1v0ds 2.4 connection of unused pins connect the unused pins as follows. table 2-1. connection of unused pins pin recommended connection p0a 0 to p0a 3 leave open. p0b 0 to p0b 3 p0c 0 to p0c 3 p0d 0 to p0d 3 p0e 0 to p0e 3 connect to gnd (input mode). p1a 0 to p1a 2 p1b 0 /int connect to gnd. rem leave open. 2.5 notes on using the reset and int pins in addition to the functions shown in 2. pin functions , the reset and int pins also have the function of setting a test mode (for ic testing) in which the internal operations of the pd17p246 are tested. when a voltage higher than v dd is applied to either of these pins, the test mode is set. this means that, even during normal operation, the pd17p246 may be set in the test mode if noise exceeding v dd is applied. for example, if the wiring length of the reset or int pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. ? connect diode with low v f between v dd ? connect capacitor between v dd and reset/int pin and reset/int pin v dd v dd reset, int v dd v dd reset, int diode with low v f
pd17p246 14 data sheet u15215ej1v0ds 3. writing and verifying one-time prom (program memory) the program memory of the pd17p246 is one-time prom of 16,384 16 bits. to write or verify this one-time prom, the pins shown in table 3-1 are used. note that no address input pin is used. instead, the address is updated by using the clock input from the clk pin. table 3-1. pins used to write/verify program memory pin name function v pp supplies voltage when writing/verifying program memory. apply +12.5 v to this pin. v dd power supply. supply +6 v to this pin when writing/verifying program memory. clk inputs clock to update address when writing/verifying program memory. by inputting pulse four times to clk pin, address of program memory is updated. md 0 to md 3 input to select operating mode when writing/verifying program memory. d 0 to d 7 inputs/outputs 8-bit data when writing/verifying program memory. 3.1 operating mode when writing/verifying program memory the pd17p246 is set in the program memory write/verify mode when +6 v is applied to the v dd pin and +12.5 v is applied to the v pp pin after the pd17p246 has been in the reset status (v dd = 5 v, reset = 0 v) for a specific time. in this mode, the operating modes shown in table 3-2 can be set by setting the md 0 to md 3 pins. leave all the pins other than those shown in table 3-1 unconnected or connect them to gnd via a pull-down resistor (470 ? ). (see pin configuration (2) prom programming mode.) table 3-2. setting operating mode setting of operating mode operating mode v pp v dd md 0 md 1 md 2 md 3 +12.5 v +6 v h l h l program memory address 0 clear mode l h h h write mode l l h h verify mode h h h program inhibit mode : don t care (l or h)
pd17p246 15 data sheet u15215ej1v0ds 3.2 program memory writing procedure the program memory is written at high speed in the following procedure. (1) pull down the pins not used to gnd via a resistor. keep the clk pin low. (2) supply 5 v to the v dd pin. keep the v pp pin low. (3) supply 5 v to the v pp pin after waiting for 10 s. (4) set the program memory address 0 clear mode by using the mode setting pins. (5) supply +6 v to v dd and +12.5 v to v pp . (6) set the program inhibit mode. (7) write data to the program memory in the 1-ms write mode. (8) set the program inhibit mode. (9) set the verify mode. if the data have been written to the program memory, proceed to (10). if not, repeat steps (7) through (9). (10) additional writing of (number of times of writing in (7) through (9): x) 1 ms. (11) set the program inhibit mode. (12) input a pulse to the clk pin four times to update the program memory address (+1). (13) repeat steps (7) through (12) up to the last address. (14) set the 0 clear mode of the program memory address. (15) change the voltages on the v dd and v pp pins to 5 v. (16) turn off power. the following figure illustrates steps (2) through (12) above. write repeated x time verify additional write address increment md 3 md 2 md 1 md 0 d 0 to d 7 clk gnd v dd v dd v dd +1 gnd v dd v pp v pp reset data input data output data input hi-z hi-z hi-z hi-z
pd17p246 16 data sheet u15215ej1v0ds 3.3 program memory reading procedure (1) pull down the pins not used to gnd via a resistor. keep the clk pin low. (2) supply 5 v to the v dd pin. keep the v pp pin low. (3) supply 5 v to the v pp pin after waiting for 10 s. (4) set the program memory address 0 clear mode by using the mode setting pins. (5) supply +6 v to v dd and +12.5 v to v pp . (6) set the program inhibit mode. (7) set the verify mode. data of each address is output sequentially each time the clock pulse is input to the clk pin four times. (8) set the program inhibit mode. (9) set the program memory address 0 clear mode. (10) change the voltage on the v dd and v pp pins to 5 v. (11) turn off power. the following figure illustrates steps (2) through (9) above. hi-z hi-z "l" md 3 md 2 md 1 md 0 d 0 to d 7 clk gnd v dd v dd v pp v pp v dd gnd v dd +1 reset data output data output one cycle
pd17p246 17 data sheet u15215ej1v0ds 4. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd 0.3 to +7.0 v prom power supply v pp 0.3 to +13.5 v input voltage v i 0.3 to v dd + 0.3 v output voltage v o 0.3 to v dd + 0.3 v output current, high note i oh rem pin peak value 36.0 ma rms value 24.0 ma 1 pin (p0e or p1a pin) peak value 7.5 ma rms value 5.0 ma total of p0e, p1a pins peak value 22.5 ma rms value 15.0 ma output current, low note i ol 1 pin (p0b, p0c, p0d, peak value 7.5 ma p0e, p1a, or rem pin) rms value 5.0 ma total of p0b, p0c, p0d, peak value 22.5 ma rem pins rms value 15.0 ma total of p0e, p1a pins peak value 30.0 ma rms value 20.0 ma operating temperature t a 40 to +85 c storage temperature t stg 65 to +150 c power dissipation p d t a = 85 c 180 mw note the rms value should be calculated as follows: [rms value] = [peak value] duty caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
pd17p246 18 data sheet u15215ej1v0ds recommended operating ranges (t a = ?0 to +85 c, v dd = 2.2 to 3.6 v) parameter symbol conditions min. typ. max. unit supply voltage v dd1 f x = 1 mhz high-speed mode 2.2 3.6 v (instruction execution time: 16 s) v dd2 f x = 4 mhz high-speed mode (instruction execution time: 4 s) v dd3 f x = 8 mhz normal mode (instruction execution time: 4 s) v dd4 high-speed mode 2.7 3.6 v (instruction execution time: 2 s) oscillation frequency f x rf x = f x /2 or f x 1.0 4.0 8.0 mhz rf x = 2f x 3.5 4.0 4.5 mhz operating temperature t a 40 +25 +85 c low-voltage detector note t cy 3.5 32 s note reset if the status of v dd = 2.05 v (typ.) lasts for 1 ms or longer. program hang-up does not occur even if the voltage drops, until the reset function is effected. a resonator may stop oscillating before the reset function is effected if normal operation under the low voltage is not guaranteed. remark the region indicated by the broken lines in the above figure is the guaranteed operating range in the high-speed mode. f x vs v dd 0.4 2 1 3 4 4.5 5 6 7 8 9 10 2 0 2.2 3 3.6 4 (mhz) 2.7 (normal mode) system clock f x (mhz) operation guaranteed area supply voltage v dd (v)
pd17p246 19 data sheet u15215ej1v0ds system clock oscillator characteristics (t a = 40 to +85 c, v dd = 2.2 to 3.6 v) resonator recommended item conditions min. typ. max. unit constants ceramic oscillation frequency 1.0 4.0 8.0 mhz resonator (f x ) note 1 oscillation after v dd reached min. 4 ms stabilization time note 2 in oscillation voltage range notes 1. the oscillation frequency only indicates the oscillator characteristics. 2. the oscillation stabilization time is necessary for oscillation to be stabilized after v dd application or stop mode release. caution to use a system clock oscillator, perform the wiring in the area enclosed by the dotted line in the above figure as follows, to avoid adverse wiring capacitance influences: keep wiring length as short as possible. do not cross a signal line with some other signal lines. do not route the wiring in the vicinity of lines through which a large current flows. always keep the oscillator capacitor ground at the same potential as gnd. do not ground the capacitor to a ground pattern, through which a large current flows. do not extract signals from the oscillator. x in x out
pd17p246 20 data sheet u15215ej1v0ds recommended oscillator constant ceramic resonator (t a = 40 to +85 c) recommended oscillation frequency manufacturer part number circuit constant (pf) voltage range (v dd ) remarks (mhz) c1 c2 min. max. murata mfg. co., ltd. csbla1m00j58-b0 1.0 120 120 2.0 3.6 csbfb1m00j58-r1 cstls2m00g56-b0 2.0 on-chip capacitor cstcc2m00g56-r0 cstls3m00g53-b0 3.0 cstcc3m00g53-r0 cstls4m00g53-b0 4.0 cstcr4m00g53-r0 cstls6m00g53-b0 6.0 cstcr6m00g53-r0 cstls8m00g53-b0 8.0 cstce8m00g52-r0 tdk fcr4.0mc5 4.0 2.3 3.6 on-chip capacitor fcr6.0mc5 6.0 fcr8.0mc5 8.0 external circuit example caution the oscillator constant is a reference value based on evaluation in specific environments by the resonator manufacturer. if the oscillator characteristics need to be optimized in the actual application, request the resonator manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. the internal operation conditions of the pd17p246 must be within the specifications of the dc and ac characteristics. x in x out c2 c1
pd17p246 21 data sheet u15215ej1v0ds dc characteristics (t a = ?0 to +85 c, v dd = 2.2 to 3.6 v) parameter symbol conditions min. typ. max. unit input voltage, high v ihi1 reset, int 0.80v dd v dd v v ih2 p0a, p0b, p0c, p0d 0.70v dd v dd v v ih3 p0e, p1a, p1b 0.70v dd v dd v input voltage, low v il1 reset, int 0 0.2v dd v v il2 p0a, p0b, p0c, p0d 0 0.3v dd v v il3 p0e, p1a, p1b 0 0.3v dd v input leakage current, high i lih p0a, p0b, p0c, p0d, p0e, v ih = v dd 3.0 a p1a, p1b 0 /int, reset w/o pull-down resistor input leakage current, low i lil p0e, p1a, p1b 0 /int v il = 0 v ?.0 a w/o pull-up resistor internal pull-up resistor r 1 p0e, p1a, p1b, reset (pulled up) 25 50 100 k ? r 2 p0a, p0b, p0c, p0d 100 200 400 k ? internal pull-down resistor r 3 p1a, p1b 25 50 100 k ? output current, high i oh rem v oh = 1.0 v, ? ?3 ?4 ma v dd = 3 v output voltage, high v oh p0e, p1a, rem i oh = ?.5 ma v dd ?0.3 v dd v output voltage, low v ol1 p0b, p0c, p0d, rem i ol = 0.5 ma 0 0.3 v v ol2 p0e, p1a i ol = 1.5 ma 0 0.3 v data retention characteristics v dddr reset = low level or stop mode1.3 3.6 v low-voltage detection v dt reset pin pulled down, v dt = v dd 2.05 2.2 v voltage ram retention detection v id v id = v dd , ramflag = 0 (rf21h.0), 1.65 1.8 v voltage t a = ? 10 to +60 c supply current note i dd1 operating mode v dd = 3 v 10% f x = 1 mhz 0.55 1.1 ma (high-speed) f x = 4 mhz 1.0 2.0 ma f x = 8 mhz 1.3 2.6 ma i dd2 operating mode v dd = 3 v 10% f x = 1 mhz 0.5 1.0 ma (low-speed) f x = 4 mhz 0.75 1.5 ma f x = 8 mhz 0.9 1.8 ma i dd3 halt mode v dd = 3 v 10% f x = 1 mhz 0.4 0.8 ma f x = 4 mhz 0.5 1.0 ma f x = 8 mhz 0.6 1.2 ma i dd4 stop mode v dd = 3 v 10% 2.0 20.0 a built-in poc t a = 25 c 2.0 5.0 a note this does not include the current that flows through the internal pull-up resistors.
pd17p246 22 data sheet u15215ej1v0ds ac characteristics (t a = ?0 to +85 c, v dd = 2.2 to 3.6 v) parameter symbol conditions min. typ. max. unit cpu clock cycle time note t cy1 v dd = 2.2 to 3.6 v 3.4 33 s (instruction execution time) t cy2 v dd = 2.7 to 3.6 v 1.9 33 s int high-/low-level width t inth ,20 s t intl reset low-level width t rsl 10 s note the cpu clock cycle time (instruction execution time) is determined by the oscillation frequency of the resonator connected and sysck (rf: address 02h) of the register file. the figure below shows the cpu clock cycle time t cy vs. supply voltage v dd characteristics. t cy vs v dd 2 1 3 4 5 6 7 8 9 10 33 40 2 01 3 4 3.4 1.9 2.2 2.7 3.6 operation guaranteed area cpu clock cycle time tc y ( s) supply voltage v dd (v) dc programming characteristics (t a = 25 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v) parameter symbol conditions min. typ. max. unit input voltage, high v ih1 other than clk 0.7v dd v dd v v ih2 clk v dd 0.5 v dd v input voltage, low v il1 other than clk 0 0.3v dd v v il2 clk 0 0.4 v input leakage current i li v in = v il or v ih 10 a output voltage, high v oh i oh = 1 ma v dd 1.0 v output voltage, low v ol i ol = 1.6 ma 0.4 v v dd supply current i dd 30 ma v pp supply current i pp md 0 = v il , md 1 = v ih 30 ma cautions 1. keep v pp to within +13.5 v including overshoot. 2. apply v dd before v pp and turns it off after v pp .
pd17p246 23 data sheet u15215ej1v0ds ac programming characteristics (t a = 25 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v) parameter symbol conditions min. typ. max. unit address setup time note (to md 0 )t as 2 s md 1 setup time (to md 0 )t m1s 2 s data setup time (to md 0 )t ds 2 s address hold time note (from md 0 )t ah 2 s data hold time (from md 0 )t dh 2 s data output float delay time from md 0 t df 0 130 ns v pp setup time (to md 3 )t vps 2 s v dd setup time (to md 3 )t vds 2 s initial program pulse width t pw 0.95 1.0 1.05 ms additional program pulse width t opw 0.95 21.0 ms md 0 setup time (to md 1 )t mos 2 s data output delay time from md 0 t dv md 0 = md 1 = v il 1 s md 1 hold time (from md 0 )t m1h t m1h + t m1r 50 s2 s md 1 recovery time (from md 0 )t m1r 2 s program counter reset time t pcr 10 s clk input high-, low-level width t xh , t xl 0.125 s clk input frequency f x 4.19 mhz initial mode set time t i 2 s md 3 setup time (to md 1 )t m3s 2 s md 3 hold time (from md 1 )t m3h 2 s md 3 setup time (to md 0 )t m3sr when program memory is read 2 s data output delay time from address note t dad when program memory is read 2 s data output hold time from address note t had when program memory is read 0 130 ns md 3 hold time (from md 0 )t m3hr when program memory is read 2 s data output float delay time from md 3 t dfr when program memory is read 2 s reset setup time t res 10 s note the internal address increment (+1) is performed on the rising edge of the 3rd clock, where 4 clocks comprise one cycle. the internal clock is not connected to a pin.
pd17p246 24 data sheet u15215ej1v0ds program memory write timing program memory read timing v pp v pp v dd gnd v dd +1 v dd v dd gnd clk d 0 to d 7 md 0 md 1 md 2 md 3 t res t vps t vds t xh t xl t as t ah t dh t ds t opw t df t dv t mos t m1r t dh t ds t pw t i t m3h t m1h t m1s t pcr t m3s data input data output data input data input hi-z data output data output t m3sr t pcr t dv t i t xl t dad t had t vds t vps t xh t m3hr t dfr v pp v pp v dd gnd v dd +1 v dd v dd gnd clk d 0 to d 7 md 0 md 1 "l" md 2 md 3 t res
pd17p246 25 data sheet u15215ej1v0ds 5. package drawing s s h j t i g d e f c b k p l u n item b c i l m n 30-pin plastic ssop (7.62 mm (300)) a k d e f g h j p 30 16 115 a detail of lead end m m t millimeters 0.65 (t.p.) 0.45 max. 0.13 0.5 6.1 0.2 0.10 9.85 0.15 0.17 0.03 0.1 0.05 0.24 1.3 0.1 8.1 0.2 1.2 + 0.08 ? 0.07 1.0 0.2 3 + 5 ? 3 0.25 0.6 0.15 u note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. s30mc-65-5a4-2
pd17p246 26 data sheet u15215ej1v0ds 6. recommended soldering conditions the pd17p246 should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.html) table 6-1. surface mounting type soldering conditions pd17p246m1mc-5a4: 30-pin plastic ssop (7.62 mm (300)) recommended condition soldering method soldering conditions symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-103-2 (at 210 c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 seconds max. vp15-103-2 (at 200 c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, ws60-103-1 preheating temperature: 120 c max. (package surface temperature), exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) note after opening the dry peak, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating).
pd17p246 27 data sheet u15215ej1v0ds in-circuit emulator ie-17k, ie-17k-et note 1 appendix development tools to develop the programs for the pd17p246, the following development tools are available. hardware name remarks ie-17k and ie-17k-et are the in-circuit emulators used in common with the 17k series microcontroller. ie-17k and ie-17k-et are connected to a pc-9800 series or ibm pc/at tm compatible machines as the host machine with rs-232c. by using these in-circuit emulators with a system evaluation board (em board) corresponding to the product, the emulators can emulate the product. a higher level debugging environment can be provided by using man-machine interface simplehost tm . em board this is an em board for pd17246 subseries. it can be used alone to evaluate a system (em-17246 note 2 ) or in combination with an in-circuit emulator for debugging. emulation probe ep-17k30gs is an emulation probe for 17k series 30-pin ssop (mc-5a4). when used (ep-17k30gs) with ev-9500gt-30 note 3 , it connects an em board to the target system. conversion adapter the ev-9500gt-30 is a conversion adapter for the 30-pin ssop (mc-5a4). it is used to (ev-9500gt-30 note 3 ) connect the ep-17k30gs and target system. prom programmer af-9706, af-9708, and af-9709 are prom programmers corresponding to pd17p246. (af-9706 note 4 , af-9708 note 4 , by connecting program adapter pa-17p246 to this prom programmer, pd17p246 can be af-9709 note 4 ) programmed. program adapter pa-17p236 are adapters that is used to program pd17p246, and is used in combination (pa-17p236) with af-9706, af-9708, or af-9709. notes 1. low-cost model: external power supply type 2. this is a product of naito densei machida mfg. co., ltd. for details, consult naito densei machida mfg. co., ltd. (tel: +81-45-475-4191). 3. two ev-9500gt-30 are supplied with the ep-17k30gs. five ev-9500gt-30 are optionally available as a set. 4. these are products of ando electric co., ltd. for details, consult ando electric co., ltd. (tel: +81-53- 576-1560).
pd17p246 28 data sheet u15215ej1v0ds software name outline host machine os supply part number medium 17k assembler pc-9800 japanese windows tm 3.5" 2hd saa13ra17k (ra17k) series ibm pc/at japanese windows 3.5" 2hc sab13ra17k compatible machine english windows sbb13ra17k device file pc-9800 japanese windows 3.5" 2hd saa13as17246 (as17246) series ibm pc/at japanese windows 3.5" 2hc sab13as17246 compatible machine english windows sbb13as17246 support pc-9800 japanese windows 3.5" 2hd saa13id17k software series ( simplehost ) ibm pc/at japanese windows 3.5" 2hc sab13id17k compatible machine english windows sbb13id17k the ra17k is an assembler common to the 17k series products. when developing the program of devices, ra17k is used in combination with a device file (as17246). the as17246 is a device file for pd17240, 17241, 17242, 17243, 17244, 17245, and 17246 and is used in combination with an assembler for the 17k series (ra17k). simplehost is a software package that enables man-machine interface on the windows when a program is developed by using an in-circuit emulator and a personal computer.
pd17p246 29 data sheet u15215ej1v0ds notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd17p246 30 data sheet u15215ej1v0ds [memo]
pd17p246 31 data sheet u15215ej1v0ds regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j03.4 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 sucursal en espa ? a madrid, spain tel: 091-504 27 87 v ? lizy-villacoublay, france tel: 01-30-67 58 00 succursale fran ? aise filiale italiana milano, italy tel: 02-66 75 41 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 tyskland filial taeby, sweden tel: 08-63 80 820 united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
pd17p246 simplehost is a trademark of nec electronics corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of february, 2003. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":

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